1. Field of the Invention
The present disclosure relates to a method for creating mask data, a program, an information processing apparatus, and a method for manufacturing a mask.
2. Description of the Related Art
In order to fabricate a semiconductor device, an exposure apparatus illuminates a mask and projects images of patterns on the mask onto a wafer to transfer the patterns to the wafer. In order to accurately transfer the patterns to the wafer, it is known to use mask patterns on which process proximity effect correction (PPC) has been performed. The PPC is a technique that includes optical proximity effect correction and that corrects patterns on a mask while taking into consideration the effects of development of resists and etching of a wafer in processing steps.
In Japanese Patent Laid-Open No. 2005-84101, it is described that each of elements (cells) included in a circuit pattern having a certain electrical function is subjected to the PPC in advance and saved as a library. Furthermore, it is described that when patterns on a mask are to be created by arranging a plurality of cells selected from libraries adjacent to one another, a process proximity effect generated in boundary portions of the cells is corrected again. In doing so, the time taken to complete calculation may be reduced compared to when mask patterns are created by arranging a plurality of cells that have not been subjected to correction and then the PPC is performed on all the mask patterns.
In Michael C. Smayling et al. “Low k1 Logic Design using Gridded Design Rules”, Proc. of SPIE Vol. 6925 (2008), a method for fabricating a circuit pattern called “1D layout technique” is described. In this technique, first, a line-and-space (L/S) pattern of a single pitch is formed on a wafer, and then a plurality of positions are exposed to light though hole patterns. As a result, part of the L/S pattern is cut, and thus a circuit pattern is fabricated. The exposure in this technique is technically easier than in the case of using a two-dimensional pattern that extends both in a vertical direction and in a horizontal direction. In this technique, as in the invention described in Japanese Patent Laid-Open No. 2005-84101, a method for creating mask patterns by arranging a plurality of cells subjected to the PPC and performing the PPC again on boundary portions of the cells is used. The area of each cell included in patterns used in the 1D layout technique is small. When mask patterns are created by arranging a large number of cells whose areas are small adjacent to one another, the areas of boundary portions of the cells occupy most of the areas of the mask patterns. Therefore, when the PPC is again performed on the boundary portions of the small cells subjected to the PPC as in the invention described in Japanese Patent Laid-Open No. 2005-84101, the time taken to complete the calculation of the PPC in the boundary portions becomes long, thereby making the effect of reducing the calculation time less effective.
In calculation adopting only the optical proximity effect correction, the calculation time is shorter than in the case of the PPC, which also includes calculation for the development and the etching, but since the effects of the development and the etching are not taken into consideration, mask patterns are not sufficiently corrected.